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Bookly Micro
4 Megabit (512 K x 8/256 K x 16) Flash Memory PA 29L V400T/B
3.0 Volt-Only Boot Block
DEVICE FEATURES
3/4 Single Power Supply - Voltage Range: 3.0 to 3.6 volt for both read and write operations 3/4 Sector Architecture - Byte Mode (512K x 8): One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, and seven 64Kbyte sectors - Word Mode (256K x 16): One 8-Kword, two 4-Kword, one 16-Kword, and seven 32Kword sectors 3/4 Top or Bottom Boot Block Configuration 3/4 Read Access Time - Access time: 55, 70, 90 and 120 ns 3/4 Power Consumption - Automatic sleep mode current: 200 nA - Standby mode current: 200 nA - Read current: 7 mA - Program/Erase current: 30 mA 3/4 Erase Features - Chip Erase Capability - Sector Protection: Using hardware method to lock a sector and prevent any program or erase operations within that sector. Sectors can be locked in-system or via programming equipment. Temporary Sector Unprotect feature allows code changes in previously locked sectors. 3/4 Erase Suspend/Erase Resume - Suspends an erase operation to read data from, or program data to a sector that is not being erased, then resumes the erase operation 3/4 Unlock Bypass Program - Reduce overall programming time when issuing multiple program command sequences 3/4 Embedded Algorithms - Embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors - Embedded program algorithm automatically writes and verifies data at specified addresses 3/4 End-of-Program or End-of-Erase Software Detection - Data# Polling - Toggle Bit 3/4 End-of-Program or End-of-Erase Hardware Detection - Ready/Busy# Pin (RY/BY#) 3/4 Hardware Reset (RESET#) - Hardware method to reset the device to reading array data 3/4 JEDEC Standard - Pin-out and software compatible with single-power supply Flash memory 3/4 High Reliability: - Endurance cycles: 1K (Typical) - Data retention at 125C: 10-y ear 3/4 Pac k ag e Op t i o n - 48- pin TSOP - 44- pin SO
This preliminary data sheet contains product specifications which are subject to change without notice.
PA 29L V400B/T
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PA 29L V400T/B
PRODUCT DESCRIPTION
The PA29LV400B/T is a 4 Mbit, 3.0 volt-only Flash memory organized in 524,288 bytes or 262,144 words. The word-wide data (x16) appears on DQ15-DQ0 and the byte-wide data (x8) appears on DQ7-DQ0. This device can be programmed in-system using 3.0-volt single VCC supply. No VPP is required for write or erase operation. The device can also be programmed in standard EPROM programmers. The device offers access times of 55, 70, 90 and 120 ns. The device has separate control signals, chip enable (CE#), write enable (WE#) and output enable (OE#), to eliminate bus contention. The device requires a 3.0-volt single power supply for both read and write operations. Both the program and erase operations are performed using the internally generated high voltages. The device has command set that is compatible with the JEDEC single-power-supply Flash standard. The write cycles latch addresses and data needed for programming and erase operations. To read data from the device is similar to reading from other Flash or EPROM devices. The programming operation occurs by executing the program command sequence. This initiates the Embedded Program Algorithm, which is an internal algorithm that automatically times the program pulse widths and verifies the proper cell margin. The Unlock Bypass Mode facilitates a faster programming time by issuing two write cycles (instead of four write cycles) to program data. The erase operation occurs by executing the erase command sequence. This initiates the Embedded Erase Algorithm, which is an internal algorithm that automatically pre-programs the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (Toggle Bit) status bits. After a program or erase cycle has been completed, the device is ready to read array data or to accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. Hardware data protection feature includes a low VCC detector that automatically inhibits write operation during power transition. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved during insystem operation or via programming equipment. The Erase Suspend feature allows the user to put erase on hold for any period of time to read data from, or program data to any sector that is not selected for erasure. The hardware RESET# pin will terminate any operation in progress and reset the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device in this case. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Both modes reduce greatly the power consumption. The device is offered in package types of 44pin SO and 48-pin TSOP.
This preliminary data sheet contains product specifications which are subject to change without notice.
PA 29L V400B/T
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PA 29L V400T/B
ORDERING INFORMATION Standard Products
The order number is defined by a combination of the following elements. PA 29L V400 B -70R E C
Temperature Range C = Commercial (0C to 70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) Package Type E = 48-Pin Thin Small Outline Package (TSOP), Standard Pin-out (TS048) F = 48-Pin Thin Small Outline Package (TSOP), Reverse Pin-out (TSR048) S = 44-Pin Small Outline Package (SO044)
KGD = Known Good Die
Speed 55R 70R 90R 12R
Option = 55ns = 70ns = 90ns = 120ns
Boot Code Sector Architecture T = Top Sector B = Bottom Sector Device Number/Description
PA29LV400
4 Megabit (512K x 8-Bit /256K x 16-Bit) Flash Memory 3.0-Volt only Read, Program and Erase
Valid Combinations for TSOP and SO Packages
PA29LV400T-55R PA29LV400B-55R PA29LV400T-70R PA29LV400B-70R PA29LV400T-90R PA29LV400B-90R PA29LV400T-12R PA29LV400B-12R
EC, EI, EE, FC, FI, FE, SC, SI, SE
Valid Combinations: Valid Combinations list the configurations that are supported in volume for this device.
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
Functional Block Diagram
RY/BY# VCC VSS Reset# Erase Voltage Generstor Input/Output Buffers Sector Switches DQ0-DQ15(A-1)
State Control WE# BYTE# Command register PGM Voltage Generator Chip Enable Output Enable Logic
Data Latch STB
CE# OE#
STB
Address Latch
Y-Decoder
Y-Gating
VCC Detector A0-A17
Timer
X-Decoder
Cell Matrix
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Pin Assignments
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reserve TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
Pin Assignments
NC RY/BY# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
PIN DESCRIPTION
A0-A17 = 18 addresses DQ0-DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Select 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 3.0-volt single power supply VSS = Device ground NC = Pin not connected internally
Logic Symbol
18 A0-A17 DQ0-DQ15 (A-1) 16 or 8
CE# OE# W E# RESET# BYTE# RY/BY#
This preliminary data sheet contains product specifications which are subject to change without notice.
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DEVICE OPERA TION
The device operations are initiated through internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, and the address and data information that is needed to execute the command. The contents of the register serve as inputs to the internal state machine. The outputs of state machine dictate the function of the device. Table 1 lists the device operations, the inputs and control levels they require, and the resulting output. address function.
Read
To read array data from the outputs, the system must set the CE# and OE# pins to VIL. CE# is the power control, which selects the device. OE# is the output control, which gates array data to the output pins. The WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set to read array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is required in this mode to obtain array data. The device remains enabled for read access until the command register contents are altered. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the
Wor d/B yte Configurat i on
The BYTE# pin controls the device data I/O pins DQ15-DQ0 to operate either in byte or word configuration. If the BYTE# pin is set at logic ` , 1' the device is in word configuration, and DQ15- DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ` , the device is in 0' byte configuration, and only data I/O pins DQ0- DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are in tri-state, and the DQ15 pin is used as an input for the LSB (A-1)
Tab l e 1. PAC29L V400B /T Dev i c e Op er at i o n
DQ8-DQ15 Operation
Read Write Standby Output Disable Reset Sector Protect Sector Unprotect Temporary Sector Unprotect
CE# OE# WE# Reset# VIL VIL VIL VIH VIH VIL X VIH X VIL VIL X VIH VIH VCC 0.3V VIH VIL VID VID VID
Addresses (Note) AIN AIN X X X Sector Address, A6=L, A1=H, A0=L Sector Address, A6=H, A1=H, A0=L AIN
DQ0-DQ7 DOUT DIN High-Z High-Z High-Z DIN DIN DIN
Byte# =VIH DOUT DIN High-Z High-Z High-Z X X DIN
Byte# =VIL DQ8-DQ14 = High-Z, DQ15= A-1 High-Z High-Z High-Z X X High-Z
VCC X 0.3V VIL VIH X VIL VIL X X VIH VIH X
VID = 12.0 0.5 V, X = Don' Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out t Notes: Addresses are A17:A0 in word mode (BYTE# = V IH), and A17:A-1 in byte mode (BYTE# = VIL).
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
standard read timings, except that if it reads an address that is within the erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume" for more information about this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset" in next section. The Read Operations table provides the read parameters, and Figure 11 shows the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. address and data values or writing them in the improper sequence resets the device to reading array data. To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must set WE# and CE# to VIL, and OE# to VIH. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for the write operations.
Reset
Writing the reset command to the device resets the device to reading array data. The address bits are don' care for this command. t The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasing begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Word/Byte Program
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 2 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. In order to ensure data integrity, the Byte Program command sequence should be reinitiated once the device has reset to reading array data. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Write Command/Command Sequence
Writing specific address and data commands or sequences into the command register initiates device operations. Table 2 defines the valid register command sequences. Writing incorrect
This preliminary data sheet contains product specifications which are subject to change without notice.
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Unlock Bypass
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles, followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 2 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the program address and the data 90h. The second cycle need only contain the data 00h. The device then returns to reading array data. Figure 1 illustrates the algorithm for the program operation. See the Erase/Program Operations table in "AC Characteristics" for parameters, and to Figure 15 for timing diagrams.
START
Write Program Command Sequence
Data Poll From System Embedded Program Algorithm in Progress Verify Data? Yes No Increment Address Last Address? Yes Programming Completed No
Note: See Table 2 for program command sequence.
Figure 1. Program Operation a hardware reset during the chip erase operation immediately terminates the operation. In order to ensure data integrity, the Chip Erase command sequence should be reinitiated once the device has returned to reading array data. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "Write Operation Status" for information about these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and Figure 16 for timing diagrams.
Chip Erase
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Then, two additional unlock write cycles are issued, followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 2 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that
Sector Erase
Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by
This preliminary data sheet contains product specifications which are subject to change without notice.
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writing two unlock cycles, followed by a set-up command. Then, two additional unlock write cycles are issued, followed by the address of the sector to be erased, and the sector erase command. Table 2 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector with an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be
START
Write Erase Command Sequence
Data Poll From System
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. In order to ensure data integrity, the Sector Erase command sequence should be reinitiated once the device has returned to reading array data. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these status bits.) Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and the Figure 16 for timing diagrams.
No Data = FFh?
Embedded Erase Algorithm in Progress
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if it is written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don' care" when writing the Erase t Suspend command. When the Erase Suspend command is written during a sector erase operation, the device
Yes Erasure Completed Notes: 1. See Table 2 for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information.
Figure 2. Erase Operation
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requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from, or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions are applied to these read and program operations. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors because the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Mode" for more information. The system must write the Erase Resume command (address bits are "don' care") to exit the t erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be set as shown in Table 5. In addition, when verifying sector protection, the sector address must appear properly on the highest order address bits (see Tables 3 and 4). Table 5 shows the remaining address bits that are don' care. After setting all t necessary bits as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can also issue the autoselect command via the command register, as shown in Table 2. This method does not require VID. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times without initiating another command sequence. When device is in word-wide configuration, the read cycles at addresses XX00h, XX03h and XX02h retrieve the manufacturer code, and the read cycle at address XX01h returns the device identification code. When device is in byte-wide configuration, the read cycles at addresses XX00h, XX06h and XX04h retrieve the manufacturer code, and the read cycle at address XX02h returns the device identification code. A read cycle containing a sector address (SA) and the address XX40h in word mode (or XX80h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 3 and 4 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
Standby Mode
When the system is not reading from or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state and are independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3V. Note that this is a more restricted voltage range than VIH. If CE# and RESET# are held at VIH, but not within VCC 0.3V, the device will be in the standby mode, but the standby current will be greater. When in either of these standby modes, the device requires standard
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification through identifier codes appearing on outputs DQ7-DQ0. This mode is primarily used for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Besides, the autoselect codes can also be accessed in-system through the command register.
This preliminary data sheet contains product specifications which are subject to change without notice.
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access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification.
tRH after the RESET# pin returns to VIH. Refer to the
AC Characteristics tables for RESET# parameters and to Figure 12 for the timing diagram.
Output Disable Mode
When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.
Automatic Sleep Mode
The automatic sleep mode minimizes device power consumption. The device enables automatically this mode when addresses are remain stable for tACC + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.
Sector Protection/Unprotection
The hardware sector protection can disable both program and erase operations in any sector. The hardware sector unprotection can re-enable both program and erase operations in previously protected sectors. To alter sector protection requires VID on the RESET# pin, which can be implemented either in-system or via programming equipment. Figure 3 shows the algorithms and Figure 21 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The device is shipped with all sectors unprotected. Perfect Device Technology Ltd. offers the option of programming and protecting sectors at its factory prior to shipping the device.
Hardware Reset Pin (RESET#)
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, sets all output pins in tri-state, and ignores all read/write commands during the period of RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated after the device is ready to accept another command sequence. This function is to ensure the data integrity. Current is reduced during the period of RESET# pulse. When RESET# is held at VSS 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.3 V, the standby current will be larger. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains at "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (i.e., the RY/BY# pin remains at "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data insystem. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 4 shows the algorithm, and Figure 20 shows the timing diagrams of this feature.
Hardware Data Protection
The command sequence with the requirement of unlock cycles for programming or erasure provides data protection against inadvertent writes (refer to Table 2 for command definitions). In addition, the following hardware data protection features can prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC powerup and power-down transitions, or from system
This preliminary data sheet contains product specifications which are subject to change without notice.
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Sector Protect Algorithm
Start PLSCNT = 1 RESET# = VID Wait 1 s
Sector Unprotect Algorithm
Protect All Sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (include remove VID from RESET#)
Start PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
First Write Cycle = 60h? Yes
No
No
First Write Cycle = 60h? Yes Set Up Sector Address No
Temporary Sector Unprotect Mode
All Sectors Protected? Yes
Sector Protect: Write 60h to Sector Address with A6 = 0, A1 = 1, A0 = 0
Set Up First Sector Address Sector Unprotect: Write 60h to Sector Address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1
Increment PLSCNT
Wait 15 is Read From Sector Address with A6 = 0
Wait 12 ms Increment PLSCNT Read From Sector Address with A6 = 1 No PLSCNT = 1000? Yes Yes Device Failed No Data = 00h? Set Up Next Sector Address
No PLSCNT = 25?No Yes Yes Device Failed Protect Another Sector? No Data = 01h?
Yes Last Sector Verified? Yes Remove VID from RESET# No
No Remove VID from RESET#
Write Reset Command
Write Reset Command Sector Unprotect Complete
Sector Protect Complete
Figure 3. In-System Sector Protect/Unprotect
Algorithms
This preliminary data sheet contains product specifications which are subject to change without notice.
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START
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
RESET # = VID (Note 1)
Data# Polling (DQ7)
The Data# Polling bit, DQ7, indicates whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device output on DQ7 is complement to the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement", or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 17, Data# Polling Timings (During Embedded Algorithms) in the "AC Characteristics" section, illustrates this timing diagram. Table 6 shows the outputs for Data# Polling
Perform Erase or Program Operations
RESET # = VIH
Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 3. All previously protected sectors are protected once again.
Figure 4. Temporary Sector Unprotect Operation noise. Noise/Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Write Inhibit Mode Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
This preliminary data sheet contains product specifications which are subject to change without notice.
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on DQ7. Figure 5 shows the Data# Polling algorithm. mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. Figures 14, 17 and 18 shows RY/BY# for reset, program, and erase operations, respectively.
Ready/Busy# (RY/BY#)
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is complete or in progress. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an opendrain output, several RY/BY# pins can be tied together in parallel and connect to VCC with a pullup resistor.
START
Toggle Bit I (DQ6)
The "Toggle Bit I" on DQ6 indicates whether an Embedded Program or Erase algorithm is complete or in progress, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erasesuspended program mode, and stops toggling once the Embedded Program algorithm is complete. Table 6 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Read DQ7-DQ0 Addr = VA
DQ7 = Data? No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA
Yes
DQ7 = Data? No FAIL
Yes
PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any nonprotected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend
This preliminary data sheet contains product specifications which are subject to change without notice.
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Toggle Bit II (DQ2)
When used with DQ6, the "Toggle Bit II" on DQ2 indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form. See also the DQ6: Toggle Bit I subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2 and DQ6 in graphical form.
START
Read DQ7-DQ0 Note 1 Read DQ7-DQ0
Toggle Bit =Toggle? Yes No DQ5=1? Yes Read DQ7-DQ0 Twice
No
Note 1,2
Toggle Bit =Toggle? Yes
No
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
Program/Erase Operation Not Complete, Write Reset Command
Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling (see text). 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1" (see text).
Figure 6. Toggle Bit Algorithm
device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
This preliminary data sheet contains product specifications which are subject to change without notice.
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this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). that the sector erase timer does not apply to the chip erase command. If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1". If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the "Sector Erase" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to make sure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To make sure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.
Exceeded Timing Limits (DQ5)
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under this condition, DQ5 produces a "1", which indicates a failure condition that the program or erase cycle was not successfully completed. In addition, the DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1". Under this condition, the device halts the operation, and when the operation has exceeded the timing limit, DQ5 produces a "1". Under above two conditions, the system must issue the reset command to return the device to reading array data.
Sector Erase Timer (DQ3)
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. Note
This preliminary data sheet contains product specifications which are subject to change without notice.
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Tab l e 2. PA29LV400T/B Co m m an d Def in i t i o n s
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Word Byte Manufacturer ID
Autoselect (Note 8) Cycles
Bus Cycles (Notes 2-5) First RA 555 AAA 555 AAA 555 AAA RD 2AA 555 2AA 555 2AA 555 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 55 555 AA AA 2AA 555 2AA 555 PA 2AA 555 2AA 555 55 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 AAA 555 AAA 555 AAA A0 20 90 X00 X00 X03 X06 X02 X04 X02 X02 Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
1 XXX F0 4 4 4 AA AA AA 55 55 55 55 55 90 90 90 90 90 7F 7F 1F
Word Byte Word Byte
Device ID, Top Boot Block Device ID, Bottom Boot Block
Word 4 555 2AA AA Byte AAA 555 Word Byte Word 4 555 AAA 555 4 Byte AAA 4 3 555 AAA 555 AAA AA AA 2AA 555 2AA
X01 2202 02 03 X01 2203 (SA) XX00 X40 XX01 (SA) X80 PA 00 01 PD
Sector Protect Verify (Note 9)
Program Unlock Bypass
Word Byte Word Byte
Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Word Byte Word Byte
2 XXX A0 2 XXX 6 6 555 AAA 555 AAA
90 XXX AA AA
1 XXX B0 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15-DQ8 are don' care for unlock and t command cycles. 5. Address bits A17-A11 are don' care for unlock and t command cycles, except when SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle.
Erase Resume (Note 13) 1 XXX 30 Legend: X = Don' care t RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17-A12 uniquely select any sector. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal.
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9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode.
This preliminary data sheet contains product specifications which are subject to change without notice.
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T a b le 3. PA 29L V400T T op Boot Block Sect or Ad d r ess T a b le
Address Range (in hexadecimal) Sector A17 A16 A15 A14 A13 A12 Sector Size (KBytes/ KWords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 (x 8) Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-77FFFh 78000h-79FFFh 7A000h-7BFFFh 7C000h-7FFFFh (x 16) Address Range 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3BFFFh 3C000h-3CFFFh 3D000h-3DFFFh 3E000h-3FFFFh
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1
0 1 0 1 0 1 0 1 1 1 1
X X X X X X X 0 1 1 1
X X X X X X X X 0 0 1
X X X X X X X X 0 1 X
Tab l e 4. PA29L V400B B o tto m B o o t B lo c k Sec to r A d d r es s Tab le
Address Range (in hexadecimal) Sector A17 A16 A15 A14 A13 A12 Sector Size (KBytes/ KWords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x 8) Address Range 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh (x 16) Address Range 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10
0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 1 1 0 0 1 1
0 0 0 0 1 0 1 0 1 0 1
0 0 0 1 X X X X X X X
0 1 1 X X X X X X X X
X 0 1 X X X X X X X X
Notes for Tables 3 and 4: Address range is A17:A-1 in byte mode and A17:A0 in word mode.
This preliminary data sheet contains product specifications which are subject to change without notice.
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Tab l e 5. PA29L V400B /T A u t o s el ec t Co d es (Hi g h Vo l t ag e Met h o d )
Description Mode CE# OE# WE# A17 to A12 X A11 A8 A5 DQ8 to A9 to A6 to A1 A0 to A10 A7 A2 DQ15 VIL VIL Manufacturer ID VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH VIH VIH VIH VIH VIH SA X X X X VID X VIL X VIH VIH VIH VIL Device ID: PA29LVF400T Word (Top Boot Block) Byte Device ID: PA29LV400B Word (Bottom Boot Block) Byte Sector Protection Verification X X VID X VIL X VIL VIH VID X VIL X VIL VIH X X X 7Fh 7Fh 1Fh DQ7 to DQ0
22h 02h X 02h
22h 03h X X 03h 01h (Protected) 00h (Unprotected)
VID X VIH X
X
X X
Notes: SA = Sector Address, X = Don' Care t
Table 6. Write Operation Status
Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspended Program DQ7 (Note2) DQ7# 0 1 DQ6 Toggle Toggle No Toggle DQ5 (Note 1) 0 0 0 DQ3 N/A 1 N/A DQ2 (Note 2) No Toggle Toggle Toggle RY/BY# 0 0 1
Erase Suspend Mode
Data DQ7#
Data Toggle
Data 0
Data N/A
Data N/A
1 0
Notes: 1. DQ5 switches to ` when an Embedded Program or Embedded Erase operation has exceeded the maximum timing 1' limits. See "DQ5: Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
This preliminary data sheet contains product specifications which are subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... -65C to 150C Ambient Temperature with Power Applied. ... ... ... ... ... ... ... ... ... ... ... ... ... ..... ........... ... ... ... -65C to 125C Voltage with Respect to Ground VCC (Note 1)... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . -0.5 V to +4.0 V A9, and RESET# (Note 2)... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . -0.5 V to +12.5 V All Other Pins (Note 1)... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..... ... ... ... ... ... .. -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3)... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 200 mA Note:
1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. Minimum DC input voltage on pins A9, and RESET# is -0.5 V. During voltage transitions, A9, and RESET# may overshoot V SS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V, which may overshoot to 14.0 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
2.
3.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended period may affect device reliability.
20 ns +0.8 V - 0.5 V 20 ns
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V
- 2.0 V 20 ns
20 ns
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (T A)... ..... .... ... 0C to 70C Industrial (I) Devices Ambient Temperature (T A)... ... ..... -40C to 85C Extended (E) Devices Ambient Temperature (T A)... ... ... -55C to 125C VCC Supply Voltages VCC for regulated voltage range... .. 3.0 V to 3.6 V VCC for full voltage range... ... ... ... .. 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
This preliminary data sheet contains product specifications which are subject to change without notice.
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DC CHARACTERISTICS CMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current Test Conditions VIN=VSS to VCC, VCC=VCC max VCC=VCC max; A9=12.5V VOUT=VSS to VCC, VCC=VCC max CE# = VIL, OE# = VIH, 5 MHz Byte Mode 1 MHz CE# = VIL, OE# = VIH, 5 MHz Word Mode 1 MHz CE#=VIL, OE#=VIH CE# and Reset#=VCC0.3V Reset#=VSS0.3V -0.5 0.7 x VCC VCC=3.3V IOL=4.0mA, VCC=VCC min IOH=-2.0mA, VCC=VCC min IOH=-100A, VCC=VCC min 0.85VCC VCC-0.4 11.5 7 2 7 2 30 0.2 0.2 0.2 Min Typ Max 1.0 35 1.0 12 4 12 4 50 5 5 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA mA mA mA A A A V V V V V V
ICC1
VCC Active Read Current (Note 1)
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2
VCC Active Write Current (Note 2, 3, 5) VCC Standby Current (Note 2) VCC Reset Current (Note 2)
Automatic Sleep Mode (Notes 2, 4) VIH=VCC0.3V; VIL=VSS0.3V Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. 5. Not 100% tested.
This preliminary data sheet contains product specifications which are subject to change without notice.
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TEST CONDITIONS
3.3V
Table 7. Test Specifications
2.7K
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance)
55 70
90, 120 1TTL gate
Unit
Device Under Test
30 5
100
pF ns V V V
CL
6.2K
Input Rise and Fall Times Input Pulse Levels Input Timing measurement reference levels Output timing measurement reference levels
0.0~3.0 1.5 1.5
Note: Diodes are IN3064 or equivalent
Figure 9. Test Setup
KEY TO SWITCHING WAVEFORMS
Waveform Inputs Steady Outputs
Changing from H to L
Changing from L to H
Don' care, Any Change Permitted t
Changing, State Unknown
Does Not Apply
Center Line is high Impedance State (High Z)
3.0V
Input 1.5V
Measurement Level
1.5V Output
0.0V
Figure 10. Input Waveforms and Measurement Levels AC CHARACTERISTICS Read Operations
This preliminary data sheet contains product specifications which are subject to change without notice.
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Parameter JEDEC Std Description Test Setup Min CE#=VIL OE#=VIL OE#=VIL Max Max Max Max Max Speed Options 55 55 55 55 30 25 25 70 70 70 70 30 25 25 90 90 90 90 35 30 30 120 120 120 120 50 30 30 Unit ns ns ns ns ns ns
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ
tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE tOE tDF tDF
Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1)
Notes: 1. Not 100% tested. 2. See Figure 9 and Table 7 for test specifications.
tRC Addresses CE# Addresses Stable tACC tCE OE# tOEH WE# HIGH Z tOH HIGH Z tDF tOE
Outputs
Output Valid
RESET# RY/BY#
0V
Figure 11. Read Timing
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC CHARACTERISTICS Hardware Reset (Reset#)
Parameter JEDEC Std Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) Reset# Low to Standby Mode BY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options Unit 20 500 500 50 20 0 s ns ns ns s ns
tREADY tREADY tRP tRH tRPD tRB
Note: Not 100% tested.
RY/BY#
CE#,OE#
tRH
RESET#
tRP tREADY
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
RY/BY#
tREADY tRB
CE#,OE#
RESET#
tRP
Figure 12. Reset# Timings
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC Characteristics Word/Byte Configuration (Byte#)
Parameter JEDEC Std Description CE# to Byte# Switching Low or High Byte# Switching Low to Output High Z Byte# Switching High to Output Active Max Max Min 25 55 25 70 Speed Options 55 70 5 30 90 30 120 90 120 Unit ns ns ns
tELFL / tELFH tFLQZ tFHQV
CE# OE#
BYTE#
Data Output (DQ0-DQ14) Data Output (DQ0-DQ7) Address Input
BYTE# Switching from word to byte mode
DQ0-DQ14 tELFL DQ15/A-1
DQ15 Output
tFLQZ tELFH BYTE#
BYTE# Switching from byte to word mode
DQ0-DQ14
Data Output (DQ0-DQ7) Address Input
Data Output (DQ0-DQ14) DQ15 Output
DQ15/A-1
tFHQV
Figure 13. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
OE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications
Figure 14. BYTE# Timings for Write Operations
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
AC Characteristics Erase/Program Operations
Parameter JEDEC Std Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note Byte 2) Word Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min 35 35 30 13 16 0.7 50 0 90 45 35 45 35 0 0 0 0 0 35 50 Speed Options 55 55 70 70 0 45 45 50 50 90 90 120 120 ns ns ns ns ns ns ns ns ns ns ns s sec ns ns ns Unit
tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2
tWC tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
This preliminary data sheet contains product specifications which are subject to change without notice.
PA29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC Addresses 555h
tAS PA tAH PA PA
CE# tCH OE# tWHWH1 tWPH tDS Data tDH PD tBUSY RY/BY# Status DOUT
tWP WE# tCS
A0h
tRB
VCC
tVCS
NOTES: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 15. Program Operation Timings
This preliminary data sheet contains product specifications which are subject to change without notice.
PA29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE# tCH tCS tWP WE# tDS Data tDH 55h 30h
10 for chip Erase
OE#
tWPH
tWHWH2
In Progress Complete
tBUSY
tRB
RY/BY#
tVCS VCC
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status") 2. Illustration shows device in word mode.
Figure 16. Chip/Sector Erase Operation Timings
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 Complement Complement True Valid Data High Z tDF tOE VA VA
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
High Z
Note: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 17. Data# Polling Timings (During Embedded Algorithms)
tRC Addresses VA tACC CE# tCH OE# tOEH WE# DQ6/DQ2 RY/BY# High Z tBUSY tOE tDF tOH
Valid Status Valid Status Valid Status Valid Status
VA
VA
VA
tCE
(first read)
(second read)
(stops toggling)
Note: VA=Valid address; not required for DQ6. Illustration shows first two status cycles after command sequence, last status read cycle and array data read cycle.
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
This preliminary data sheet contains product specifications which are subject to change without notice.
PA29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase
Erase Suspend
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: The system may use OE# and CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 19. DQ2 vs. DQ6 Temporary Sector Unprotect
Parameter JEDEC S Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min td
All Speed Options Unit 500 4 ns s
tVIDR tRSP
Note: Not 100% tested
12V RESET# 0 or 3V CE# 0 or 3V Program or Erase Command Sequence tVIDR
tVIDR
WE# tRSP RY/BY#
Figure 20. Temporary Sector Unprotect Timing Diagram
This preliminary data sheet contains product specifications which are subject to change without notice.
PA29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid*
Data
60h
60h
Sector Protect: 15 us Sector Unprotect: 12ms
Status
1s
CE#
WE#
OE#
* For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0.
Figure 21. Sector Protect/Unprotect Timing Diagram
This preliminary data sheet contains product specifications which are subject to change without notice.
PA 29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations
Parameter JEDEC Std Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 35 30 13 16 0.7 45 35 45 35 0 0 0 0 0 35 50 Speed Options 55 55 70 70 0 45 45 50 50 90 90 120 120 Unit ns ns ns ns ns ns ns ns ns ns ns s sec
tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2
tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2
Sector Erase Operation (Note 2)
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
This preliminary data sheet contains product specifications which are subject to change without notice.
PA 29L V400B/T
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PA 29L V400T/B
AC CHARACTERISTICS
555 for Program 2AA for erase
PA for Program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tDS Data tRH RESET# A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tDH tCPH tWHWH1 or 2 tBUSY tAS tAH
DQ7#
DOUT
RY/BY#
Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example.
Figure 22. Alternate CE# Controlled Write Operation Timings
This preliminary data sheet contains product specifications which are subject to change without notice.
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PA 29L V400T/B
Erase and Programming Performance
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Byte Mode (Note 3) Word Mode Typ (Note 1) 0.7 11 13 16 6.9 4.2 416 512 20.7 12.6 Max (Note 2) 15 Unit s s s s s s Excludes system level Overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)
Notes: 1. Typical program and erase times assume the following conditions: 25 C, 3.0 V VCC. Additionally, typical programming assumes checkerboard pattern. 2. Under worst-case conditions of 90C, VCC = 2.7 V (3.0 V for regulated speed options). 3. The typical chip programming time is considerably less than the maximum chip programming time listed because most bytes programs are faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 2 for further information on command definitions.
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Latchup Characteristics
Description Input voltage with respect to VSS on all pins except I/O pins (Including A9, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0V -1.0V -100mA Max 12.5V VCC + 1.0V +100mA
Notes: Includes all pins except VCC Test conditions: VCC =3.0V, one pin at a time.
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TSOP and SO Pin Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN=0 VOUT=0 VIN=0 Typ Max Unit 6 8.5 7.5 7.5 12 9 pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0MHz.
This preliminary data sheet contains product specifications which are subject to change without notice.
PA 29L V400B/T
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